aom: Introduce CONFIG_QUANT_MATRIX

From c95bb8b927d8431f9fdf080960934869a8878f61 Mon Sep 17 00:00:00 2001
From: Jerome Jiang <[EMAIL REDACTED]>
Date: Thu, 24 Aug 2023 10:06:11 -0400
Subject: [PATCH] Introduce CONFIG_QUANT_MATRIX

It can be used to disable quant matrices to reduce binary size.

Shared lib size reduction:

 - linux build: 4605048 -> 4187208
 - arm64 build: 2760216 -> 2326528

QM will only be disabled when both CONFIG_QUANT_MATRIX=0 and
CONFIG_AV1_DECODER=0 because we want to keep the decoder compliance.

Change-Id: I0502b150110a251dba85e3a160b4d606ebc3010c
---
 av1/av1_cx_iface.c                    |  5 +++++
 av1/common/quant_common.c             | 13 ++++++++++++-
 build/cmake/aom_config_defaults.cmake |  3 +++
 3 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/av1/av1_cx_iface.c b/av1/av1_cx_iface.c
index d82ffcb398..37ee8e7eac 100644
--- a/av1/av1_cx_iface.c
+++ b/av1/av1_cx_iface.c
@@ -1837,6 +1837,11 @@ static aom_codec_err_t ctrl_set_enable_qm(aom_codec_alg_priv_t *ctx,
                                           va_list args) {
   struct av1_extracfg extra_cfg = ctx->extra_cfg;
   extra_cfg.enable_qm = CAST(AV1E_SET_ENABLE_QM, args);
+#if !CONFIG_QUANT_MATRIX
+  if (extra_cfg.enable_qm) {
+    ERROR("QM can't be enabled with CONFIG_QUANT_MATRIX=0.");
+  }
+#endif
   return update_extra_cfg(ctx, &extra_cfg);
 }
 static aom_codec_err_t ctrl_set_qm_y(aom_codec_alg_priv_t *ctx, va_list args) {
diff --git a/av1/common/quant_common.c b/av1/common/quant_common.c
index b0976287ef..6204c0eff1 100644
--- a/av1/common/quant_common.c
+++ b/av1/common/quant_common.c
@@ -274,13 +274,16 @@ const qm_val_t *av1_get_qmatrix(const CommonQuantParams *quant_params,
              : quant_params->gqmatrix[NUM_QM_LEVELS - 1][0][qm_tx_size];
 }
 
+#if CONFIG_QUANT_MATRIX || CONFIG_AV1_DECODER
 #define QM_TOTAL_SIZE 3344
 // We only use wt_matrix_ref[q] and iwt_matrix_ref[q]
 // for q = 0, ..., NUM_QM_LEVELS - 2.
 static const qm_val_t wt_matrix_ref[NUM_QM_LEVELS - 1][2][QM_TOTAL_SIZE];
 static const qm_val_t iwt_matrix_ref[NUM_QM_LEVELS - 1][2][QM_TOTAL_SIZE];
+#endif
 
 void av1_qm_init(CommonQuantParams *quant_params, int num_planes) {
+#if CONFIG_QUANT_MATRIX || CONFIG_AV1_DECODER
   for (int q = 0; q < NUM_QM_LEVELS; ++q) {
     for (int c = 0; c < num_planes; ++c) {
       int current = 0;
@@ -306,6 +309,10 @@ void av1_qm_init(CommonQuantParams *quant_params, int num_planes) {
       }
     }
   }
+#else
+  (void)quant_params;
+  (void)num_planes;
+#endif  // CONFIG_QUANT_MATRIX || CONFIG_AV1_DECODER
 }
 
 /* Provide 15 sets of quantization matrices for chroma and luma
@@ -320,6 +327,8 @@ void av1_qm_init(CommonQuantParams *quant_params, int num_planes) {
    distances. Matrices for QM level 15 are omitted because they are
    not used.
  */
+
+#if CONFIG_QUANT_MATRIX || CONFIG_AV1_DECODER
 static const qm_val_t iwt_matrix_ref[NUM_QM_LEVELS - 1][2][QM_TOTAL_SIZE] = {
   {
       { /* Luma */
@@ -12873,4 +12882,6 @@ static const qm_val_t wt_matrix_ref[NUM_QM_LEVELS - 1][2][QM_TOTAL_SIZE] = {
         33, 33, 32, 32, 32, 32, 34, 33, 33, 33, 32, 32, 32, 32, 34, 33, 33, 33,
         32, 32, 32, 32 },
   },
-};
\ No newline at end of file
+};
+
+#endif  // CONFIG_QUANT_MATRIX || CONFIG_AV1_DECODER
diff --git a/build/cmake/aom_config_defaults.cmake b/build/cmake/aom_config_defaults.cmake
index 5b01ea270b..980dfb9327 100644
--- a/build/cmake/aom_config_defaults.cmake
+++ b/build/cmake/aom_config_defaults.cmake
@@ -85,6 +85,9 @@ set_aom_config_var(CONFIG_AV1_TEMPORAL_DENOISING 0
 set_aom_config_var(CONFIG_MULTITHREAD 1 "Multithread support.")
 set_aom_config_var(CONFIG_OS_SUPPORT 0 "Internal flag.")
 set_aom_config_var(CONFIG_PIC 0 "Build with PIC enabled.")
+set_aom_config_var(CONFIG_QUANT_MATRIX 1
+                   "Build with quantization matrices for AV1 encoder."
+                   "AV1 decoder is always built with quantization matrices.")
 set_aom_config_var(CONFIG_REALTIME_ONLY 0
                    "Build for RTC-only. See aomcx.h for all disabled features.")
 set_aom_config_var(CONFIG_RUNTIME_CPU_DETECT 1 "Runtime CPU detection support.")