aom: x86/*: exclude 1:4/4:1 fns w/CONFIG_REALTIME_ONLY

From 3076bbe33897ed332a12ca54d7addb3b9ce9d0ed Mon Sep 17 00:00:00 2001
From: James Zern <[EMAIL REDACTED]>
Date: Tue, 18 Jun 2024 17:43:42 -0700
Subject: [PATCH] x86/*: exclude 1:4/4:1 fns w/CONFIG_REALTIME_ONLY

This fixes some -Wmissing-prototypes warnings.

Bug: aomedia:3416
Change-Id: I483d0e00ac42b7f9b87e81a5f2c6d5d56c6ea554
---
 aom_dsp/x86/highbd_sad_avx2.c              | 57 +++++++++++++++-------
 aom_dsp/x86/highbd_variance_sse2.c         | 36 ++++++++++++++
 aom_dsp/x86/masked_sad4d_ssse3.c           |  3 ++
 aom_dsp/x86/masked_sad_intrin_avx2.c       |  6 +++
 aom_dsp/x86/masked_sad_intrin_ssse3.c      |  6 +++
 aom_dsp/x86/masked_variance_intrin_ssse3.c |  6 +++
 aom_dsp/x86/sad4d_avx2.c                   | 14 ++++--
 aom_dsp/x86/variance_sse2.c                |  4 +-
 8 files changed, 108 insertions(+), 24 deletions(-)

diff --git a/aom_dsp/x86/highbd_sad_avx2.c b/aom_dsp/x86/highbd_sad_avx2.c
index 8fb08b30e..68bc928ec 100644
--- a/aom_dsp/x86/highbd_sad_avx2.c
+++ b/aom_dsp/x86/highbd_sad_avx2.c
@@ -267,18 +267,14 @@ static AOM_FORCE_INLINE unsigned int aom_highbd_sad128xN_avx2(
                                           2 * ref_stride);                   \
   }
 
-HIGHBD_SADMXN_AVX2(16, 4)
 HIGHBD_SADMXN_AVX2(16, 8)
 HIGHBD_SADMXN_AVX2(16, 16)
 HIGHBD_SADMXN_AVX2(16, 32)
-HIGHBD_SADMXN_AVX2(16, 64)
 
-HIGHBD_SADMXN_AVX2(32, 8)
 HIGHBD_SADMXN_AVX2(32, 16)
 HIGHBD_SADMXN_AVX2(32, 32)
 HIGHBD_SADMXN_AVX2(32, 64)
 
-HIGHBD_SADMXN_AVX2(64, 16)
 HIGHBD_SADMXN_AVX2(64, 32)
 HIGHBD_SADMXN_AVX2(64, 64)
 HIGHBD_SADMXN_AVX2(64, 128)
@@ -286,17 +282,21 @@ HIGHBD_SADMXN_AVX2(64, 128)
 HIGHBD_SADMXN_AVX2(128, 64)
 HIGHBD_SADMXN_AVX2(128, 128)
 
+#if !CONFIG_REALTIME_ONLY
+HIGHBD_SADMXN_AVX2(16, 4)
+HIGHBD_SADMXN_AVX2(16, 64)
+HIGHBD_SADMXN_AVX2(32, 8)
+HIGHBD_SADMXN_AVX2(64, 16)
+#endif  // !CONFIG_REALTIME_ONLY
+
 HIGHBD_SAD_SKIP_MXN_AVX2(16, 8)
 HIGHBD_SAD_SKIP_MXN_AVX2(16, 16)
 HIGHBD_SAD_SKIP_MXN_AVX2(16, 32)
-HIGHBD_SAD_SKIP_MXN_AVX2(16, 64)
 
-HIGHBD_SAD_SKIP_MXN_AVX2(32, 8)
 HIGHBD_SAD_SKIP_MXN_AVX2(32, 16)
 HIGHBD_SAD_SKIP_MXN_AVX2(32, 32)
 HIGHBD_SAD_SKIP_MXN_AVX2(32, 64)
 
-HIGHBD_SAD_SKIP_MXN_AVX2(64, 16)
 HIGHBD_SAD_SKIP_MXN_AVX2(64, 32)
 HIGHBD_SAD_SKIP_MXN_AVX2(64, 64)
 HIGHBD_SAD_SKIP_MXN_AVX2(64, 128)
@@ -304,6 +304,13 @@ HIGHBD_SAD_SKIP_MXN_AVX2(64, 128)
 HIGHBD_SAD_SKIP_MXN_AVX2(128, 64)
 HIGHBD_SAD_SKIP_MXN_AVX2(128, 128)
 
+#if !CONFIG_REALTIME_ONLY
+HIGHBD_SAD_SKIP_MXN_AVX2(16, 64)
+HIGHBD_SAD_SKIP_MXN_AVX2(32, 8)
+HIGHBD_SAD_SKIP_MXN_AVX2(64, 16)
+#endif  // !CONFIG_REALTIME_ONLY
+
+#if !CONFIG_REALTIME_ONLY
 unsigned int aom_highbd_sad16x4_avg_avx2(const uint8_t *src, int src_stride,
                                          const uint8_t *ref, int ref_stride,
                                          const uint8_t *second_pred) {
@@ -315,6 +322,7 @@ unsigned int aom_highbd_sad16x4_avg_avx2(const uint8_t *src, int src_stride,
 
   return get_sad_from_mm256_epi32(&sad);
 }
+#endif  // !CONFIG_REALTIME_ONLY
 
 unsigned int aom_highbd_sad16x8_avg_avx2(const uint8_t *src, int src_stride,
                                          const uint8_t *ref, int ref_stride,
@@ -362,6 +370,7 @@ unsigned int aom_highbd_sad16x32_avg_avx2(const uint8_t *src, int src_stride,
   return sum;
 }
 
+#if !CONFIG_REALTIME_ONLY
 unsigned int aom_highbd_sad16x64_avg_avx2(const uint8_t *src, int src_stride,
                                           const uint8_t *ref, int ref_stride,
                                           const uint8_t *second_pred) {
@@ -395,6 +404,7 @@ unsigned int aom_highbd_sad32x8_avg_avx2(const uint8_t *src, int src_stride,
   }
   return get_sad_from_mm256_epi32(&sad);
 }
+#endif  // !CONFIG_REALTIME_ONLY
 
 unsigned int aom_highbd_sad32x16_avg_avx2(const uint8_t *src, int src_stride,
                                           const uint8_t *ref, int ref_stride,
@@ -444,6 +454,7 @@ unsigned int aom_highbd_sad32x64_avg_avx2(const uint8_t *src, int src_stride,
   return sum;
 }
 
+#if !CONFIG_REALTIME_ONLY
 unsigned int aom_highbd_sad64x16_avg_avx2(const uint8_t *src, int src_stride,
                                           const uint8_t *ref, int ref_stride,
                                           const uint8_t *second_pred) {
@@ -463,6 +474,7 @@ unsigned int aom_highbd_sad64x16_avg_avx2(const uint8_t *src, int src_stride,
   }
   return get_sad_from_mm256_epi32(&sad);
 }
+#endif  // !CONFIG_REALTIME_ONLY
 
 unsigned int aom_highbd_sad64x32_avg_avx2(const uint8_t *src, int src_stride,
                                           const uint8_t *ref, int ref_stride,
@@ -663,18 +675,14 @@ static AOM_FORCE_INLINE void aom_highbd_sadMxNxD_avx2(
                              sad_array);                                      \
   }
 
-HIGHBD_SAD_MXNX4D_AVX2(16, 4)
 HIGHBD_SAD_MXNX4D_AVX2(16, 8)
 HIGHBD_SAD_MXNX4D_AVX2(16, 16)
 HIGHBD_SAD_MXNX4D_AVX2(16, 32)
-HIGHBD_SAD_MXNX4D_AVX2(16, 64)
 
-HIGHBD_SAD_MXNX4D_AVX2(32, 8)
 HIGHBD_SAD_MXNX4D_AVX2(32, 16)
 HIGHBD_SAD_MXNX4D_AVX2(32, 32)
 HIGHBD_SAD_MXNX4D_AVX2(32, 64)
 
-HIGHBD_SAD_MXNX4D_AVX2(64, 16)
 HIGHBD_SAD_MXNX4D_AVX2(64, 32)
 HIGHBD_SAD_MXNX4D_AVX2(64, 64)
 HIGHBD_SAD_MXNX4D_AVX2(64, 128)
@@ -682,17 +690,21 @@ HIGHBD_SAD_MXNX4D_AVX2(64, 128)
 HIGHBD_SAD_MXNX4D_AVX2(128, 64)
 HIGHBD_SAD_MXNX4D_AVX2(128, 128)
 
+#if !CONFIG_REALTIME_ONLY
+HIGHBD_SAD_MXNX4D_AVX2(16, 4)
+HIGHBD_SAD_MXNX4D_AVX2(16, 64)
+HIGHBD_SAD_MXNX4D_AVX2(32, 8)
+HIGHBD_SAD_MXNX4D_AVX2(64, 16)
+#endif  // !CONFIG_REALTIME_ONLY
+
 HIGHBD_SAD_SKIP_MXNX4D_AVX2(16, 8)
 HIGHBD_SAD_SKIP_MXNX4D_AVX2(16, 16)
 HIGHBD_SAD_SKIP_MXNX4D_AVX2(16, 32)
-HIGHBD_SAD_SKIP_MXNX4D_AVX2(16, 64)
 
-HIGHBD_SAD_SKIP_MXNX4D_AVX2(32, 8)
 HIGHBD_SAD_SKIP_MXNX4D_AVX2(32, 16)
 HIGHBD_SAD_SKIP_MXNX4D_AVX2(32, 32)
 HIGHBD_SAD_SKIP_MXNX4D_AVX2(32, 64)
 
-HIGHBD_SAD_SKIP_MXNX4D_AVX2(64, 16)
 HIGHBD_SAD_SKIP_MXNX4D_AVX2(64, 32)
 HIGHBD_SAD_SKIP_MXNX4D_AVX2(64, 64)
 HIGHBD_SAD_SKIP_MXNX4D_AVX2(64, 128)
@@ -700,21 +712,30 @@ HIGHBD_SAD_SKIP_MXNX4D_AVX2(64, 128)
 HIGHBD_SAD_SKIP_MXNX4D_AVX2(128, 64)
 HIGHBD_SAD_SKIP_MXNX4D_AVX2(128, 128)
 
-HIGHBD_SAD_MXNX3D_AVX2(16, 4)
+#if !CONFIG_REALTIME_ONLY
+HIGHBD_SAD_SKIP_MXNX4D_AVX2(16, 64)
+HIGHBD_SAD_SKIP_MXNX4D_AVX2(32, 8)
+HIGHBD_SAD_SKIP_MXNX4D_AVX2(64, 16)
+#endif  // !CONFIG_REALTIME_ONLY
+
 HIGHBD_SAD_MXNX3D_AVX2(16, 8)
 HIGHBD_SAD_MXNX3D_AVX2(16, 16)
 HIGHBD_SAD_MXNX3D_AVX2(16, 32)
-HIGHBD_SAD_MXNX3D_AVX2(16, 64)
 
-HIGHBD_SAD_MXNX3D_AVX2(32, 8)
 HIGHBD_SAD_MXNX3D_AVX2(32, 16)
 HIGHBD_SAD_MXNX3D_AVX2(32, 32)
 HIGHBD_SAD_MXNX3D_AVX2(32, 64)
 
-HIGHBD_SAD_MXNX3D_AVX2(64, 16)
 HIGHBD_SAD_MXNX3D_AVX2(64, 32)
 HIGHBD_SAD_MXNX3D_AVX2(64, 64)
 HIGHBD_SAD_MXNX3D_AVX2(64, 128)
 
 HIGHBD_SAD_MXNX3D_AVX2(128, 64)
 HIGHBD_SAD_MXNX3D_AVX2(128, 128)
+
+#if !CONFIG_REALTIME_ONLY
+HIGHBD_SAD_MXNX3D_AVX2(16, 4)
+HIGHBD_SAD_MXNX3D_AVX2(16, 64)
+HIGHBD_SAD_MXNX3D_AVX2(32, 8)
+HIGHBD_SAD_MXNX3D_AVX2(64, 16)
+#endif  // !CONFIG_REALTIME_ONLY
diff --git a/aom_dsp/x86/highbd_variance_sse2.c b/aom_dsp/x86/highbd_variance_sse2.c
index 676208bfc..ca45c324f 100644
--- a/aom_dsp/x86/highbd_variance_sse2.c
+++ b/aom_dsp/x86/highbd_variance_sse2.c
@@ -152,10 +152,13 @@ VAR_FN(16, 16, 16, 8)
 VAR_FN(16, 8, 8, 7)
 VAR_FN(8, 16, 8, 7)
 VAR_FN(8, 8, 8, 6)
+
+#if !CONFIG_REALTIME_ONLY
 VAR_FN(8, 32, 8, 8)
 VAR_FN(32, 8, 8, 8)
 VAR_FN(16, 64, 16, 10)
 VAR_FN(64, 16, 16, 10)
+#endif  // !CONFIG_REALTIME_ONLY
 
 #undef VAR_FN
 
@@ -382,6 +385,23 @@ DECLS(sse2)
     return (var >= 0) ? (uint32_t)var : 0;                                     \
   }
 
+#if CONFIG_REALTIME_ONLY
+#define FNS(opt)                         \
+  FN(128, 128, 16, 7, 7, opt, (int64_t)) \
+  FN(128, 64, 16, 7, 6, opt, (int64_t))  \
+  FN(64, 128, 16, 6, 7, opt, (int64_t))  \
+  FN(64, 64, 16, 6, 6, opt, (int64_t))   \
+  FN(64, 32, 16, 6, 5, opt, (int64_t))   \
+  FN(32, 64, 16, 5, 6, opt, (int64_t))   \
+  FN(32, 32, 16, 5, 5, opt, (int64_t))   \
+  FN(32, 16, 16, 5, 4, opt, (int64_t))   \
+  FN(16, 32, 16, 4, 5, opt, (int64_t))   \
+  FN(16, 16, 16, 4, 4, opt, (int64_t))   \
+  FN(16, 8, 16, 4, 3, opt, (int64_t))    \
+  FN(8, 16, 8, 3, 4, opt, (int64_t))     \
+  FN(8, 8, 8, 3, 3, opt, (int64_t))      \
+  FN(8, 4, 8, 3, 2, opt, (int64_t))
+#else  // !CONFIG_REALTIME_ONLY
 #define FNS(opt)                         \
   FN(128, 128, 16, 7, 7, opt, (int64_t)) \
   FN(128, 64, 16, 7, 6, opt, (int64_t))  \
@@ -402,6 +422,7 @@ DECLS(sse2)
   FN(32, 8, 16, 5, 3, opt, (int64_t))    \
   FN(16, 64, 16, 4, 6, opt, (int64_t))   \
   FN(64, 16, 16, 6, 4, opt, (int64_t))
+#endif  // CONFIG_REALTIME_ONLY
 
 FNS(sse2)
 
@@ -549,6 +570,20 @@ DECLS(sse2)
     return (var >= 0) ? (uint32_t)var : 0;                                     \
   }
 
+#if CONFIG_REALTIME_ONLY
+#define FNS(opt)                       \
+  FN(64, 64, 16, 6, 6, opt, (int64_t)) \
+  FN(64, 32, 16, 6, 5, opt, (int64_t)) \
+  FN(32, 64, 16, 5, 6, opt, (int64_t)) \
+  FN(32, 32, 16, 5, 5, opt, (int64_t)) \
+  FN(32, 16, 16, 5, 4, opt, (int64_t)) \
+  FN(16, 32, 16, 4, 5, opt, (int64_t)) \
+  FN(16, 16, 16, 4, 4, opt, (int64_t)) \
+  FN(16, 8, 16, 4, 3, opt, (int64_t))  \
+  FN(8, 16, 8, 3, 4, opt, (int64_t))   \
+  FN(8, 8, 8, 3, 3, opt, (int64_t))    \
+  FN(8, 4, 8, 3, 2, opt, (int64_t))
+#else  // !CONFIG_REALTIME_ONLY
 #define FNS(opt)                       \
   FN(64, 64, 16, 6, 6, opt, (int64_t)) \
   FN(64, 32, 16, 6, 5, opt, (int64_t)) \
@@ -566,6 +601,7 @@ DECLS(sse2)
   FN(32, 8, 16, 5, 3, opt, (int64_t))  \
   FN(16, 64, 16, 4, 6, opt, (int64_t)) \
   FN(64, 16, 16, 6, 4, opt, (int64_t))
+#endif  // CONFIG_REALTIME_ONLY
 
 FNS(sse2)
 
diff --git a/aom_dsp/x86/masked_sad4d_ssse3.c b/aom_dsp/x86/masked_sad4d_ssse3.c
index d2181a5a9..08847c815 100644
--- a/aom_dsp/x86/masked_sad4d_ssse3.c
+++ b/aom_dsp/x86/masked_sad4d_ssse3.c
@@ -260,9 +260,12 @@ MASKSAD8XN_SSSE3(8)
 MASKSAD8XN_SSSE3(4)
 MASKSAD4XN_SSSE3(8)
 MASKSAD4XN_SSSE3(4)
+
+#if !CONFIG_REALTIME_ONLY
 MASKSAD4XN_SSSE3(16)
 MASKSADMXN_SSSE3(16, 4)
 MASKSAD8XN_SSSE3(32)
 MASKSADMXN_SSSE3(32, 8)
 MASKSADMXN_SSSE3(16, 64)
 MASKSADMXN_SSSE3(64, 16)
+#endif  // !CONFIG_REALTIME_ONLY
diff --git a/aom_dsp/x86/masked_sad_intrin_avx2.c b/aom_dsp/x86/masked_sad_intrin_avx2.c
index 8800af7a4..a8097bf4a 100644
--- a/aom_dsp/x86/masked_sad_intrin_avx2.c
+++ b/aom_dsp/x86/masked_sad_intrin_avx2.c
@@ -192,12 +192,15 @@ MASKSADMXN_AVX2(64, 64)
 MASKSADMXN_AVX2(64, 128)
 MASKSADMXN_AVX2(128, 64)
 MASKSADMXN_AVX2(128, 128)
+
+#if !CONFIG_REALTIME_ONLY
 MASKSADMXN_AVX2(4, 16)
 MASKSADMXN_AVX2(16, 4)
 MASKSADMXN_AVX2(8, 32)
 MASKSADMXN_AVX2(32, 8)
 MASKSADMXN_AVX2(16, 64)
 MASKSADMXN_AVX2(64, 16)
+#endif  // !CONFIG_REALTIME_ONLY
 
 static INLINE unsigned int highbd_masked_sad8xh_avx2(
     const uint8_t *src8, int src_stride, const uint8_t *a8, int a_stride,
@@ -381,9 +384,12 @@ HIGHBD_MASKSADMXN_AVX2(64, 64)
 HIGHBD_MASKSADMXN_AVX2(64, 128)
 HIGHBD_MASKSADMXN_AVX2(128, 64)
 HIGHBD_MASKSADMXN_AVX2(128, 128)
+
+#if !CONFIG_REALTIME_ONLY
 HIGHBD_MASKSADMXN_AVX2(4, 16)
 HIGHBD_MASKSADMXN_AVX2(16, 4)
 HIGHBD_MASKSADMXN_AVX2(8, 32)
 HIGHBD_MASKSADMXN_AVX2(32, 8)
 HIGHBD_MASKSADMXN_AVX2(16, 64)
 HIGHBD_MASKSADMXN_AVX2(64, 16)
+#endif  // !CONFIG_REALTIME_ONLY
diff --git a/aom_dsp/x86/masked_sad_intrin_ssse3.c b/aom_dsp/x86/masked_sad_intrin_ssse3.c
index 0c75a8be9..ee56d3327 100644
--- a/aom_dsp/x86/masked_sad_intrin_ssse3.c
+++ b/aom_dsp/x86/masked_sad_intrin_ssse3.c
@@ -84,12 +84,15 @@ MASKSAD8XN_SSSE3(8)
 MASKSAD8XN_SSSE3(4)
 MASKSAD4XN_SSSE3(8)
 MASKSAD4XN_SSSE3(4)
+
+#if !CONFIG_REALTIME_ONLY
 MASKSAD4XN_SSSE3(16)
 MASKSADMXN_SSSE3(16, 4)
 MASKSAD8XN_SSSE3(32)
 MASKSADMXN_SSSE3(32, 8)
 MASKSADMXN_SSSE3(16, 64)
 MASKSADMXN_SSSE3(64, 16)
+#endif  // !CONFIG_REALTIME_ONLY
 
 static INLINE unsigned int masked_sad_ssse3(const uint8_t *src_ptr,
                                             int src_stride,
@@ -275,12 +278,15 @@ HIGHBD_MASKSADMXN_SSSE3(8, 8)
 HIGHBD_MASKSADMXN_SSSE3(8, 4)
 HIGHBD_MASKSAD4XN_SSSE3(8)
 HIGHBD_MASKSAD4XN_SSSE3(4)
+
+#if !CONFIG_REALTIME_ONLY
 HIGHBD_MASKSAD4XN_SSSE3(16)
 HIGHBD_MASKSADMXN_SSSE3(16, 4)
 HIGHBD_MASKSADMXN_SSSE3(8, 32)
 HIGHBD_MASKSADMXN_SSSE3(32, 8)
 HIGHBD_MASKSADMXN_SSSE3(16, 64)
 HIGHBD_MASKSADMXN_SSSE3(64, 16)
+#endif  // !CONFIG_REALTIME_ONLY
 
 static INLINE unsigned int highbd_masked_sad_ssse3(
     const uint8_t *src8, int src_stride, const uint8_t *a8, int a_stride,
diff --git a/aom_dsp/x86/masked_variance_intrin_ssse3.c b/aom_dsp/x86/masked_variance_intrin_ssse3.c
index e23faef7a..81c40cdfc 100644
--- a/aom_dsp/x86/masked_variance_intrin_ssse3.c
+++ b/aom_dsp/x86/masked_variance_intrin_ssse3.c
@@ -126,12 +126,15 @@ MASK_SUBPIX_VAR8XH_SSSE3(8)
 MASK_SUBPIX_VAR8XH_SSSE3(4)
 MASK_SUBPIX_VAR4XH_SSSE3(8)
 MASK_SUBPIX_VAR4XH_SSSE3(4)
+
+#if !CONFIG_REALTIME_ONLY
 MASK_SUBPIX_VAR4XH_SSSE3(16)
 MASK_SUBPIX_VAR_SSSE3(16, 4)
 MASK_SUBPIX_VAR8XH_SSSE3(32)
 MASK_SUBPIX_VAR_SSSE3(32, 8)
 MASK_SUBPIX_VAR_SSSE3(64, 16)
 MASK_SUBPIX_VAR_SSSE3(16, 64)
+#endif  // !CONFIG_REALTIME_ONLY
 
 static INLINE __m128i filter_block(const __m128i a, const __m128i b,
                                    const __m128i filter) {
@@ -704,12 +707,15 @@ HIGHBD_MASK_SUBPIX_VAR_SSSE3(8, 8)
 HIGHBD_MASK_SUBPIX_VAR_SSSE3(8, 4)
 HIGHBD_MASK_SUBPIX_VAR4XH_SSSE3(8)
 HIGHBD_MASK_SUBPIX_VAR4XH_SSSE3(4)
+
+#if !CONFIG_REALTIME_ONLY
 HIGHBD_MASK_SUBPIX_VAR4XH_SSSE3(16)
 HIGHBD_MASK_SUBPIX_VAR_SSSE3(16, 4)
 HIGHBD_MASK_SUBPIX_VAR_SSSE3(8, 32)
 HIGHBD_MASK_SUBPIX_VAR_SSSE3(32, 8)
 HIGHBD_MASK_SUBPIX_VAR_SSSE3(16, 64)
 HIGHBD_MASK_SUBPIX_VAR_SSSE3(64, 16)
+#endif  // !CONFIG_REALTIME_ONLY
 
 static INLINE __m128i highbd_filter_block(const __m128i a, const __m128i b,
                                           const __m128i filter) {
diff --git a/aom_dsp/x86/sad4d_avx2.c b/aom_dsp/x86/sad4d_avx2.c
index 46fc1747b..324b14223 100644
--- a/aom_dsp/x86/sad4d_avx2.c
+++ b/aom_dsp/x86/sad4d_avx2.c
@@ -142,12 +142,10 @@ static AOM_FORCE_INLINE void aom_sadMxNx3d_avx2(
     aom_sadMxNx3d_avx2(m, n, src, src_stride, ref, ref_stride, res);           \
   }
 
-SADMXN_AVX2(32, 8)
 SADMXN_AVX2(32, 16)
 SADMXN_AVX2(32, 32)
 SADMXN_AVX2(32, 64)
 
-SADMXN_AVX2(64, 16)
 SADMXN_AVX2(64, 32)
 SADMXN_AVX2(64, 64)
 SADMXN_AVX2(64, 128)
@@ -155,6 +153,11 @@ SADMXN_AVX2(64, 128)
 SADMXN_AVX2(128, 64)
 SADMXN_AVX2(128, 128)
 
+#if !CONFIG_REALTIME_ONLY
+SADMXN_AVX2(32, 8)
+SADMXN_AVX2(64, 16)
+#endif  // !CONFIG_REALTIME_ONLY
+
 #define SAD_SKIP_MXN_AVX2(m, n)                                             \
   void aom_sad_skip_##m##x##n##x4d_avx2(const uint8_t *src, int src_stride, \
                                         const uint8_t *const ref[4],        \
@@ -167,12 +170,10 @@ SADMXN_AVX2(128, 128)
     res[3] <<= 1;                                                           \
   }
 
-SAD_SKIP_MXN_AVX2(32, 8)
 SAD_SKIP_MXN_AVX2(32, 16)
 SAD_SKIP_MXN_AVX2(32, 32)
 SAD_SKIP_MXN_AVX2(32, 64)
 
-SAD_SKIP_MXN_AVX2(64, 16)
 SAD_SKIP_MXN_AVX2(64, 32)
 SAD_SKIP_MXN_AVX2(64, 64)
 SAD_SKIP_MXN_AVX2(64, 128)
@@ -180,6 +181,11 @@ SAD_SKIP_MXN_AVX2(64, 128)
 SAD_SKIP_MXN_AVX2(128, 64)
 SAD_SKIP_MXN_AVX2(128, 128)
 
+#if !CONFIG_REALTIME_ONLY
+SAD_SKIP_MXN_AVX2(32, 8)
+SAD_SKIP_MXN_AVX2(64, 16)
+#endif  // !CONFIG_REALTIME_ONLY
+
 static AOM_FORCE_INLINE void aom_sad16xNx3d_avx2(int N, const uint8_t *src,
                                                  int src_stride,
                                                  const uint8_t *const ref[4],
diff --git a/aom_dsp/x86/variance_sse2.c b/aom_dsp/x86/variance_sse2.c
index 5f3f89938..25143a23d 100644
--- a/aom_dsp/x86/variance_sse2.c
+++ b/aom_dsp/x86/variance_sse2.c
@@ -321,7 +321,6 @@ void aom_get_var_sse_sum_16x16_dual_sse2(const uint8_t *src_ptr, int src_stride,
 
 AOM_VAR_NO_LOOP_SSE2(4, 4, 4, 128)
 AOM_VAR_NO_LOOP_SSE2(4, 8, 5, 128)
-AOM_VAR_NO_LOOP_SSE2(4, 16, 6, 128)
 
 AOM_VAR_NO_LOOP_SSE2(8, 4, 5, 128)
 AOM_VAR_NO_LOOP_SSE2(8, 8, 6, 128)
@@ -331,13 +330,14 @@ AOM_VAR_NO_LOOP_SSE2(16, 8, 7, 128)
 AOM_VAR_NO_LOOP_SSE2(16, 16, 8, 256)
 AOM_VAR_NO_LOOP_SSE2(16, 32, 9, 512)
 
-AOM_VAR_NO_LOOP_SSE2(32, 8, 8, 256)
 AOM_VAR_NO_LOOP_SSE2(32, 16, 9, 512)
 AOM_VAR_NO_LOOP_SSE2(32, 32, 10, 1024)
 
 #if !CONFIG_REALTIME_ONLY
+AOM_VAR_NO_LOOP_SSE2(4, 16, 6, 128)
 AOM_VAR_NO_LOOP_SSE2(16, 4, 6, 128)
 AOM_VAR_NO_LOOP_SSE2(8, 32, 8, 256)
+AOM_VAR_NO_LOOP_SSE2(32, 8, 8, 256)
 AOM_VAR_NO_LOOP_SSE2(16, 64, 10, 1024)
 #endif