Optimized drawing methods(OT)

Daniel Phillips wrote:

This isn’t quite accurate either. If rendering is done to main memory but a
hardware-accelerated blit to the graphics memory is available that uses DMA
over AGP and runs in the background, then the CPU will scarcely notice the
massive blits taking place at all. However, getting all those things to come
true at once has proved to be something of a nightmare, as there are many
ways for subsystems to drop the ball due to configuration mistakes,
unimplemented features, or even design errors.

For example, AGP 8X provides 2.1 GB/sec bandwidth, while blitting 70 FPS,
1600x1200, 32 bit color requires only a little over half a GB/sec. So if
software blitting isn’t fast as heck on modern hardware, do blame the system
or the configuration, don’t blame the hardware.

Daniel

Fair enough. :slight_smile:

I get an odd picture of the inside of a x86 PC, sometimes… superfast
processors looking on forlornly, strangled to a standstill by a billion
peripherals working at cross-purposes; a mini ecosystem in silicon… I’m more
of a PC lover than anybody, but even I’m wondering if it’s time to drop the
ancient IBM baggage and design a better system from scratch.

I get an odd picture of the inside of a x86 PC, sometimes… superfast
processors looking on forlornly, strangled to a standstill by a billion
peripherals working at cross-purposes; a mini ecosystem in silicon…
I’m more of a PC lover than anybody, but even I’m wondering if it’s time
to drop the ancient IBM baggage and design a better system from scratch.

The ancient “IBM baggage” is and has been for years attached to what is
referred to as a “South bridge” chip that parks itself on the PCI bus, so
all one would need to do is remove it - not redesign it. Yes, even those
motherboards with an ISA bus are just ISA->PCI bridge chips.

All personal computers follow the CPU/front side bus/PCI buses memory
architecture, and even if you redesigned it, it’d still wind up being a
variation of that architecture.

–>Neil-------------------------------------------------------------------------------
Neil Bradley In the land of the blind, the one eyed man is not
Synthcom Systems, Inc. king - he’s a prisoner.
ICQ #29402898

Well, I suppose this is getting a little off-topic, but AMD’s Hammer
completely redefines that architecture, and it is not a variation. The north
bridge’s bridging function is replaced by Hypertransport, and the processor
intefaces directly to memory without the overhead of any bridge at all. So
the north bridge is completely gone (along with one fan, a small mercy). It
remains to be seen how well Hammers play with AGP, which, like the PCI, is
connected via hypertransport.

Regards,

DanielOn Friday 17 January 2003 03:21, Neil Bradley wrote:

The ancient “IBM baggage” is and has been for years attached to what is
referred to as a “South bridge” chip that parks itself on the PCI bus, so
all one would need to do is remove it - not redesign it. Yes, even those
motherboards with an ISA bus are just ISA->PCI bridge chips.

All personal computers follow the CPU/front side bus/PCI buses memory
architecture, and even if you redesigned it, it’d still wind up being a
variation of that architecture.